Google Adds TPU 8tx and 8i Max as TPU Customers Approach 100

Analyst(s): Brendan Burke
Publication Date: November 10, 2026

Google expanded its eighth-generation TPU family with 8tx for confidential inference and 8i Max, a dual-die package with 384 GB of HBM and 17.2 TB/s of bandwidth, six months after the generation launched. Measured against Futurum’s five-tier agentic silicon platform, the November systems close the last gap in Google’s agentic lineup.

What Is Covered in This Article:

• TPU 8tx for confidential inference, with hardware enclaves, cryptographic attestation, and PCIe link encryption on 8t silicon
• TPU 8i Max packaging two 8i dies for 384 GB of HBM, 17.2 TB/s of bandwidth, and 768 MB of on-chip SRAM
• Four eighth-generation TPU systems within one year and a TPU customer base nearing 100
• The announcement mapped against Futurum’s five-tier agentic silicon platform and the Hot Chips design targets behind the split
• TorchTPU, vLLM and SGLang serving, LLM-d 1.0, TPU Sync, and the first public TPU v7 AgentX results

The News: Google announced two additions to its eighth-generation TPU family on November 9, bringing the generation to four systems within a single year for the first time. TPU 8tx pairs the 8t training silicon, 12.6 petaflops of native FP4 compute and 216 GB of HBM, with 5th Gen AMD EPYC host CPUs that enforce hardware-level PCIe link encryption, cryptographic attestation, and secure memory enclaves. Google positions it for regulated enterprises and governments running fine-tuning, reinforcement learning, and inference on one system. “To solve the exposure problem, TPU 8tx shifts trust from software into silicon,” said Amin Vahdat, SVP and Chief Technologist for AI and Infrastructure, on the launch webcast.

TPU 8i Max doubles the 8i compute silicon in a single package, reaching 384 GB of HBM, 33% more than 8i, with 17.2 TB/s of HBM bandwidth and 768 MB of on-chip SRAM, each double the 8i figures, in the existing rack footprint.

An overhauled software slate made the hardware open to external customers. Google open-sourced TorchTPU, built with Meta’s PyTorch team, brought vLLM and SGLang support with ecosystem partners Inferact and RadixArk, shipped LLM-d 1.0 inside GKE Inference Gateway, and introduced TPU Sync, which moves an idle agent’s working memory off the accelerator. “Co-designed software delivers optimal results, but co-designed must never mean closed,” said Mark Lohmeyer, VP and GM of AI and Computing Infrastructure at Google Cloud. Lohmeyer also announced A5X general availability on the NVIDIA Vera Rubin platform and the Agent Substrate donation to the Cloud Native Computing Foundation. Vahdat said TPUs now serve nearly 100 customers, with agent-driven traffic up more than 7,800% in a year.

Google Adds TPU 8tx and 8i Max as TPU Customers Approach 100

Analyst Take: The November drop reads as a point-by-point response to the scorecard in Futurum’s Q3 State of the Market, “Agentic Silicon Becomes a Platform.” That report defined agentic silicon as a five-tier disaggregated platform co-designed around the token dynamics of high-concurrency agent sessions, and it scored Google’s April bifurcation as the first accelerator roadmap split around the definition. It also recorded a gap. Context memory had no Google product.

Each layer advanced on November 9 against a need frontier agent systems have made concrete. 8i Max doubles the decode silicon serving contexts that grow past 150K tokens, 8tx gives agents acting on regulated data a hardware trust boundary, TPU Sync and LLM-d 1.0 build context memory in software, Agent Compute Engine matches the runtime to agents that pause for hours between actions, and the Virgo fabric from Hot Chips extends the scale-out domain to 134,400 TPUs.

The layers interoperate with GPUs by design. Lohmeyer said teams can deploy identical PyTorch code and scale prefill and decode pools across mixed fleets of TPUs and GPUs behind a single endpoint through LLM-d, while A5X on Vera Rubin reached general availability on the same AI Hypercomputer and Google Distributed Cloud runs NVIDIA Blackwell for sovereign and air-gapped deployments. Both new systems remain vendor-defined for now. There is more to watch with the public AgentX record at TPU v7, pricing and availability dates unstated, and no launch partners.

TPU 8tx Turns Agent Containment Into a Hardware Property

Agent security is now a measured deficit. In Futurum’s 1H 2026 Cybersecurity Decision-Maker survey, 56% of 933 security leaders said they cannot detect or contain a compromised agent at machine speed, and Futurum forecasts agent control planes and agentic governance growing at a 48.7% CAGR through CY2030, the fastest of its 16 security segments. The silicon vendors have adjusted. When Futurum analyzed NVIDIA’s Open Agent Safety Platform in September, the sound bet was placing controls where the agent cannot reach, with the OpenShell runtime enforcing policy in software and the Sentry watchdog running on BlueField-4 DPUs that most enterprises do not own. Google applies the same principle in fewer places.

8tx makes the containment a hardware property. Link encryption, attestation, and memory enclaves are enforced by the TPU package and its 5th Gen EPYC host, where AMD Secure Encrypted Virtualization keeps model weights, prompts, and intermediate data encrypted in CPU memory and in transit, so a compliance team audits one hardware perimeter. Prevailing accelerator architectures distribute confidential computing across the GPU, the CPU, and the network adapter under a coordinating software layer, widening the surface to certify. 8tx also runs reinforcement learning and inference on the same silicon with sensitive data never leaving the enclave. Validation is the open question. Google has yet to publish an attestation audit or a third-party evaluation of the enclave design.

AMD operates the orchestration layer, whichever accelerator wins. The company says EPYC is the host CPU of choice for more than 10 leading hyperscalers and frontier AI labs across systems built on AMD Instinct GPUs, NVIDIA GPUs, and custom ASICs, a claim based on AMD’s own count. “The most capable AI systems need a CPU foundation that can match the demands of the accelerators they host,” said Dan McNamara, Senior Vice President and General Manager, Compute and Enterprise AI, AMD.

8i Max Doubles the Decode Silicon Where the Token Demand Model Concentrates

Futurum’s Q3 State of the Market built its forecast on a token demand model in which agents consume up to 15x more tokens than standard chat sessions, and decode is the bandwidth-bound stage of that load. At Hot Chips in August, TPU architects described the move to two dedicated dies a year to eliminate dark silicon and reduced the inference design brief to two ratios: more HBM bandwidth per unit of compute and a larger share of die area on SRAM. 8i met those targets with 384 MB of SRAM, triple the prior generation. Scaling FLOPs is easy and scaling interconnect is hard, in their framing, leading the memory-efficiency convergence Futurum identified across the Hot Chips 2026 program.

8i Max doubles exactly the resources that brief prioritized. Futurum has argued that agentic inference is bound by the ratio of compute to memory bandwidth, and 8i Max keeps that ratio fixed while doubling both sides, with 768 MB of SRAM keeping KV state on the die. Mid-generation performance scaling has become a packaging discipline. Vendors adding third-party inference dies to their fabrics face multi-year integration programs where Google compressed the cycle to six months. The constraint is supply-side. Doubling HBM per socket in a DRAM market Futurum expects to stay tight through 2027 puts 8i Max in competition with every other advanced package for memory.

TPU Sync and LLM-d Build the Context Memory Google Was Missing

Context memory was Google’s open flank in the Q3 scorecard, which treats the KV cache as a persistent working set needing its own home between HBM and bulk storage. Google’s answer arrived in software. TPU Sync moves an agent’s working memory off the accelerator the moment it pauses, and LLM-d 1.0 keeps prompt context cached across accelerator memory, host CPU, and storage with prefix-cache-aware routing. A posted Qwen3.5 397B AgentX configuration already runs the stack, spilling KV state to host DRAM through TPU Sync and raising decode cache hit rates from 56% to 76%. The open question is whether software matches dedicated context-memory hardware as contexts pass 150K tokens.

External demand decides what the completed platform is worth. Futurum’s AI Supply Chain model projects Anthropic deploying 3.9 GW on 8i-class TPUs in 2027, ahead of Google’s own 2.5 GW, with 8t adding 4.2 GW, roughly 10.6 GW of v8 deployments in all. The nearly 100 customers sit on top of an Anthropic agreement the Q3 report sized at roughly 1 million TPUs.

Public AgentX results posted November 9 give the platform argument third-party numbers, one generation back. TPU v7 at FP8 delivers 1.2x to 2.7x the tokens per dollar of B200, B300, and MI355X on GLM-5.2 and beats GB300 FP8 at every interactivity level on Qwen3.5 397B with llm-d disaggregated serving, staying competitive on Meta’s Muse Spark Open and Kimi K3 in ecosystem-built submissions. FP4 GPUs keep the per-dollar lead wherever a model tolerates the format, since TPU v7 has no native FP4, and the eighth generation’s native FP4 answers exactly that gap.

The customer gap now sits on the new silicon. Buyers asked for AgentX results because the benchmark resembles their production agent traffic, and no 8i, 8i Max, or 8tx submission is public yet, so the procurement case for the systems announced today rests on prior-generation data. The single-cloud objection is eroding. Google began shipping TPU systems into third-party data centers in Q2 2026, and Meta reportedly struck a multibillion-dollar agreement in February to deploy TPUs in its own facilities. TPUs have never been more prepared for customer scale. The code paths are open, the serving layer is portable, the hardware ships into third-party data centers, and the labs committing most deeply already shape their model architectures around the silicon.

What to Watch:

• Whether 8i and 8i Max submit for independent testing to compare with GB300 and Vera Rubin results
• Whether eighth-generation native FP4 closes the per-dollar lead FP4 GPUs keep over TPU v7
• Whether an AI lab, regulated enterprise, or government is named as a TPU 8tx customer in coming quarters
• Whether a Google context memory hardware product appears alongside TPU Sync’s software layer
• Whether Anthropic’s 8i-class deployments track toward the 3.9 GW Futurum models for 2027

The complete details about this announcement are available on Google’s website.

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Sources

1. Our newest TPUs: 8tx and 8i Max, built for the agentic era, Blog, November 2026
2. State of the Market Report: Semiconductors, Supply Chain, and Emerging Technology, Q3 2026

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Declaration of generative AI and AI-assisted technologies in the writing process: This content has been generated with the support of artificial intelligence technologies. Due to the fast pace of content creation and the continuous evolution of data and information, The Futurum Group and its analysts strive to ensure the accuracy and factual integrity of the information presented. However, the opinions and interpretations expressed in this content reflect those of the individual author/analyst. The Futurum Group makes no guarantees regarding the completeness, accuracy, or reliability of any information contained herein. Readers are encouraged to verify facts independently and consult relevant sources for further clarification.

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